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general description the max1393/max1396 micropower, serial-output, 12- bit, analog-to-digital converters (adcs) operate with a single power supply from +1.5v to +3.6v. these adcs feature automatic shutdown, fast wake-up, and a high- speed 3-wire interface. power consumption is only 0.734mw (v dd = +1.5v) at the maximum conversion rate of 312.5ksps. autoshutdown between conversions reduces power consumption at slower throughput rates. the max1393/max1396 require an external reference v ref that has a wide range from 0.6v to v dd . the max1393 provides one true-differential analog input that accepts signals ranging from 0 to v ref (unipolar mode) or ? ref /2 (bipolar mode). the max1396 pro- vides two single-ended inputs that accept signals rang- ing from 0 to v ref . analog conversion results are available through a 5mhz 3-wire spi-/qspi-/ microwire-/digital signal processor (dsp)-compati- ble serial interface. excellent dynamic performance, low voltage, low power, ease of use, and small pack- age sizes make these converters ideal for portable bat- tery-powered data-acquisition applications, and for other applications that demand low power consumption and minimal space. the max1393/max1396 are available in a space-saving (3mm x 3mm) 10-pin tdfn package or 10-pin ?ax package. the parts operate over the extended (-40? to +85?) and military (-55? to +125?) temper- ature ranges. applications portable datalogging data acquisition medical instruments battery-powered instruments process control features ? 312.5ksps, 12-bit successive-approximation register (sar) adcs ? single true-differential analog input channel with unipolar-/bipolar-select input (max1393) ? dual single-ended input channel with channel- select input (max1396) ? 1 lsb inl, 1 lsb dnl, no missing codes ? 2 lsb total unadjusted error (tue) ? 70db sinad at 75khz input frequency ? external reference (0.6v to v dd ) ? single-supply voltage (+1.5v to +3.6v) ? 0.915mw at 300ksps, 1.8v ? 0.305mw at 100ksps, 1.8v ? 3.1w at 1ksps, 1.8v ? < 1a shutdown current ? autoshutdown between conversions ? spi-/qspi-/microwire-/dsp-compatible, 3- or 4-wire serial interface ? small (3mm x 3mm) 10-pin tdfn or max (3mm x 5mm) package max1393/max1396 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs ________________________________________________________________ maxim integrated products 1 19-3644; rev 0; 5/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package analog inputs top mark max1393 etb -40? to +85? 10 tdfn-ep** 1-ch diff aoz max1393eub -40? to +85? 10 ?ax 1-ch diff max1393mtb* -55? to +125? 10 tdfn-ep** 1-ch diff max1393mub* -55? to +125? 10 ?ax 1-ch diff max1396 etb -40? to +85? 10 tdfn-ep** 2-ch s/e apc max1396eub* -40? to +85? 10 ?ax 2-ch s/e max1396mtb* -55? to +125? 10 tdfn-ep** 2-ch s/e max1396mub* -55? to +125? 10 ?ax 2-ch s/e autoshutdown is a trademark of maxim integrated products, inc. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. ?ax is a registered trademark of maxim integrated products, inc. typical operating circuit and pin configurations appear at end of data sheet. * future product?ontact factory for availability. ** ep = exposed pad.
max1393/max1396 2 _______________________________________________________________________________________ 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs absolute maximum ratings electrical characteristics (v dd = +1.5v to +3.6v, v ref = v dd , c ref = 0.1?, f sclk = 5mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +4v sclk, cs , oe , ch1 /ch2, uni/ bip , dout to gnd.........................................-0.3v to (v dd + 0.3v) ain+, ain-, ain1, ain2, ref to gnd ........-0.3v to (v dd + 0.3v) maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70?) 10-pin tdfn (derate 18.5mw/? above +70?) ....1481.5mw 10-pin ?ax (derate 5.6mw/? above +70?) ........444.4mw operating temperature ranges max139_e_ _...................................................-40? to +85? max139_m_ _ ................................................-55? to +125? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc accuracy (note 1) resolution 12 bits integral nonlinearity inl ? lsb differential nonlinearity dnl no missing code overtemperature ? lsb offset error 0.5 ? lsb gain error offset nulled 0.5 ? lsb total unadjusted error tue ? lsb offset-error temperature coefficient ?.004 lsb/? gain-error temperature coefficient ?.001 lsb/? channel-to-channel offset matching max1396 only ?.1 lsb channel-to-channel gain matching max1396 only ?.1 lsb input common-mode rejection cmr v cm = 0 to v dd , max1393 only ?.1 mv/v dynamic specifications (note 2) v ref = v dd = 1.6 70 v ref = v dd = 1.8?.5 69 signal-to-noise plus distortion sinad v ref = v dd = 2.5?.6 70 db v ref = v dd = 1.6 70.5 v ref = v dd = 1.8?.5 70 71 signal-to-noise ratio snr v ref = v dd = 2.5?.6 71 db total harmonic distortion thd -83 -75 dbc spurious-free dynamic range sfdr -85 -76 dbc intermodulation distortion imd f in1 = 73khz at -6.5dbfs, f in2 = 77khz at -6.5dbfs -78 db channel-to-channel crosstalk max1396 only -70 db
max1393/max1396 _______________________________________________________________________________________ 3 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs electrical characteristics (continued) (v dd = +1.5v to +3.6v, v ref = v dd , c ref = 0.1?, f sclk = 5mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units full-power bandwidth -3db point 4 mhz max1393 200 full-linear bandwidth sinad > 68db max1396 150 khz conversion rate conversion time t conv 13 clock cycles 2.6 ? throughput rate 16 clock cycles per conversion; includes power-up, acquisition, and conversion time 312.5 ksps power-up and acquisition time t acq three sclk cycles 600 ns aperture delay t ad 8ns aperture jitter t aj 30 ps serial clock frequency f clk 0.1 5.0 mhz analog inputs (ain+, ain-, ain1, ain2) unipolar 0 v ref input voltage range v in bipolar, max1393 only, (ain+ - ain-) -v ref /2 +v ref /2 v common-mode input voltage range v cm bipolar, max1393 only, [(ain+) + (ain-)] / 2 0 v dd v input leakage current channel not selected, or conversion stopped, or in shutdown mode ? ? input capacitance 16 pf reference input (ref) ref input voltage range v ref 0.6 v dd + 0.05 v ref input capacitance 24 pf ref dc leakage current 0.025 ?.5 ? ref input dynamic current 312.5ksps 20 60 ? digital inputs (sclk, cs , oe , ch1 /ch2, uni/ bip ) input-voltage low v il 0.3 x v dd v input-voltage high v ih 0.7 x v dd v input hysteresis 0.06 x v dd v input leakage current i il inputs at gnd or v dd ? ? cs , oe 1 input capacitance c in ch1 /ch2, uni/ bip 1 digital output (dout) output-voltage low v ol i sink = 2ma 0.1 x v dd v output-voltage high v oh i source = 2ma 0.9 x v dd v
max1393/max1396 4 _______________________________________________________________________________________ 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs electrical characteristics (continued) (v dd = +1.5v to +3.6v, v ref = v dd , c ref = 0.1?, f sclk = 5mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units tri-state leakage current i lt oe = v dd ? ? tri-state output capacitance c out oe = v dd 10 pf power supply positive supply voltage v dd 1.5 3.6 v v dd = 1.6v 176 200 f sample = 100ksps v dd = 3v 225 260 v dd = 1.6v 520 600 f sample = 312.5ksps v dd = 3v 710 800 power-down mode (note 4) 5 10 positive supply current (note 3) i dd power-down mode (note 5) 0.2 ?.5 ? power-supply rejection psr v dd = 1.5v to 3.6v, full-scale input (note 6) ?50 ?000 ?/v timing characteristics (v dd = +1.5v to +3.6v, v ref = v dd , c ref = 0.1?, f sclk = 5mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (figure 1) parameter symbol conditions min typ max units sclk clock period t cp 200 10,000 ns sclk pulse-width high t ch 90 ns sclk pulse-width low t cl 90 ns cs fall to sclk rise setup t css 80 ns sclk rise to cs fall ignore t cso 0ns sclk fall to dout valid t dov c load = 0 to 30pf 10 80 ns oe rise to dout disable t dod 620ns oe fall to dout enable t doe 920ns cs pulse-width high or low t csw 80 ns oe pulse-width high or low t oew 80 ns ch1 /ch2 setup time (to the first sclk) t chs max1396 only 10 ns ch1 /ch2 hold time (to the first sclk) t chh max1396 only 0 ns uni/ bip setup time (to the first sclk) t ubs max1393 only 10 ns uni/ bip hold time (to the first sclk) t ubh max1393 only 0 ns note 1: v dd = 1.5v, v ref = 1.5v, and v ain = 1.5v. note 2: v dd = 1.5v, v ref = 1.5v, v ain = 1.5v p-p , f sclk = 5mhz, f sample = 312.5ksps, and f in (sine wave) = 75khz. note 3: all digital inputs swing between v dd and gnd. v ref = v dd ,f in = 75khz sine wave, v ain = v refp-p, c load = 30pf on dout. note 4: cs = v dd , oe = uni/ bip = ch1 /ch2 = v dd or gnd, sclk is active. note 5: cs = v dd , oe = uni/ bip = ch1 /ch2 = v dd or gnd, sclk is inactive. note 6: change in v ain at code boundary 4094.5.
max1393/max1396 _______________________________________________________________________________________ 5 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs cs sclk dout oe uni/bip or ch1/ch2 t ubs t chs t ubh t chh t cso t css t cl t ch t cp t doe high-z t dov t oew t csw t dod high-z figure 1. detailed serial-interface timing diagram gnd 50pf 50pf dout dout gnd v dd a) high impedance to v oh , v ol to v oh , and v oh to high impedance b) high impedance to v ol , v oh to v ol , and v ol to high impedance 10ma 10ma figure 2. load circuits for enable/disable times
1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs max1393/max1396 6 _______________________________________________________________________________________ dnl error vs. reference voltage max1393/96 toc04 reference voltage (v) dnl error (lsb) 3.1 2.6 2.1 1.6 1.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0.6 3.6 v dd = 3.6v max dnl min dnl offset error vs. supply voltage max1393/96 toc05 supply voltage (v) offset error ( v) v ref = 1.5v temperature = +25 c -300 -200 -100 0 100 200 300 400 -400 3.3 3.0 1.8 2.1 2.4 2.7 1.5 3.6 ain1 ain2 offset error vs. temperature max1393/96 toc06 temperature ( c) offset error ( v) 95 -25 5 35 65 -300 -200 -100 0 100 200 300 400 -400 -55 125 v dd = 2.6v offset error vs. reference voltage max1393/96 toc07 reference voltage (v) offset error ( v) 3.1 1.1 1.6 2.1 2.6 -300 -200 -100 0 100 200 300 400 -400 0.6 3.6 v dd = 3.6v gain error vs. supply voltage max1393/96 toc08 supply voltage (v) gain error ( v) 3.3 3.0 1.8 2.1 2.4 2.7 -300 -200 -100 0 100 200 300 400 -400 1.5 3.6 v ref = 1.5v temperature = +25 c gain error vs. temperature max1393/96 toc09 temperature ( c) gain error ( v) 95 -25 5 35 65 -300 -200 -100 0 100 200 300 400 -400 -55 125 v dd = 2.6v ain1 ain2 t ypical operating characteristics (v dd = +1.5v, v ref = +1.5v, c ref = 0.1?, c l = 30pf, f sclk = 5mhz. t a = +25?, unless otherwise noted.) inl vs. code max1393/96 toc01 code inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = 1.5v v ref = 1.5v inl error vs. reference voltage max1393/96 toc02 reference voltage (v) inl error (lsb) 3.1 2.6 2.1 1.6 1.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0.6 3.6 v dd = 3.6v max inl min inl dnl vs. code max1393/96 toc03 code dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = 1.5v v ref = 1.5v
max1393/max1396 _______________________________________________________________________________________ 7 supply current vs. conversion rate max1393/96 toc13 f sample (ksps) supply current ( a) 300 250 200 150 100 50 200 400 600 800 0 0 350 f sclk = 5mhz, f sample = 312.5ksps ain = full scale, 75khz sine wave c l = 30pf v dd = v ref = 1.6v v dd = v ref = 3.0v shutdown current vs. supply voltage max1393/96 toc14 supply voltage (v) shutdown current ( a) 3.3 3.0 2.7 2.4 2.1 1.8 0.1 0.2 0.3 0.4 0.5 0 1.5 3.6 serial clock idle shutdown supply current vs. temperature max1393/96 toc15 temperature ( c) shutdown supply current ( a) 95 65 35 5 -25 0.4 0.8 1.2 1.6 2.0 0 -55 125 v dd = 1.8v v dd = 3.6v sclk-to-dout timing max1393/96 toc16 c load (pf) dout delay (ns) 500 400 300 200 100 10 20 30 40 50 60 70 80 90 100 0 0 600 v dd = 3.6v v dd = 1.5v fft max1393/96 toc17 frequency (khz) magnitude (db) 120 100 80 60 40 20 -100 -75 -50 -25 0 -125 0 140 160 v dd = 2.5v v ref = 2.5v f s = 312.5ksps f in = 75khz thd = -90.3db sinad = 72.1db sfdr = 93.3db sampling error vs. source impedance max1393/96 toc18 source impedance ( ? ) sampling error (lsb) 2000 1500 1000 500 -3 -2 -1 0 1 2 3 4 -4 0 2500 ain high-to-low fs transition ain low-to-high fs transition 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs gain error vs. reference voltage max1393/96 toc10 reference voltage (v) gain error ( v) 3.1 1.1 1.6 2.1 2.6 -300 -200 -100 0 100 200 300 400 -400 0.6 3.6 v dd = 3.6v supply current vs. supply voltage max1393/96 toc11 supply voltage (v) supply current ( a) 3.3 3.0 2.7 2.4 2.1 1.8 500 600 700 800 400 1.5 3.6 v ref = 1.5v, c l = 33pf f sclk = 4.8mhz, f sample = 300ksps ain = full scale, 10khz sine wave supply current vs. temperature max1393/96 toc12 temperature ( c) supply current ( a) 95 65 35 5 -25 450 500 550 600 400 -55 125 v ref = 1.5v, c l = 33pf f sclk = 4.8mhz, f sample = 300ksps ain = full scale, 10khz sine wave t ypical operating characteristics (continued) (v dd = +1.5v, v ref = +1.5v, c ref = 0.1?, c l = 30pf, f sclk = 5mhz. t a = +25?, unless otherwise noted.)
max1393/max1396 detailed description the max1393/max1396 use an input track and hold (t/h) circuit along with a sar to convert an analog input signal to a serial 12-bit digital output data stream. the serial interface provides easy interfacing to microproces- sors and dsps. figure 3 shows the simplified functional diagram for the max1393 (1 channel, true differential) and the max1396 (2 channels, single ended). true-differential analog input t/h the equivalent input circuit of figure 4 shows the max1393/max1396 input architecture, which is com- posed of a t/h, a comparator, and a switched-capacitor dac. the t/h enters its tracking mode on the falling edge of cs (while oe is held low). the positive input capacitor is connected to ain+ (max1393), or to ain1 or ain2 (max1396). the negative input capacitor is con- nected to ain- (max1393) or gnd (max1396). the t/h enters its hold mode on the 3rd falling edge of sclk 8 _______________________________________________________________________________________ 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs pin max1393 max1396 name function 11v dd positive supply voltage. connect v dd to a 1.5v to 3.6v power supply. bypass v dd to gnd with a 0.1? capacitor as close to the device as possible. 2 ain- negative analog input ? ain2 analog input channel 2 3 ain+ positive analog input ? ain1 analog input channel 1 44 gnd ground 55 ref external reference voltage input. v ref = 0.6v to (v dd + 0.05v). bypass ref to gnd with a 0.1? capacitor as close to the device as possible. 6 uni/ bip input-mode select. drive uni/ bip high to select unipolar input mode. pull uni/ bip low to select bipolar input mode. in unipolar mode, the output data is in straight binary format. in bipolar mode, the output data is in two? complement format. ? ch1 /ch2 channel-select input. pull ch1 /ch2 low to select channel 1. drive ch1 /ch2 high to select channel 2. 77 oe active-low output enable. pull oe low to enable dout. drive oe high to disable dout. connect to cs to interface with spi, qspi, and microwire devices or set low to interface with dsp devices. 88 cs active-low chip-select input. a falling edge on cs initiates power-up and acquisition. 99 dout serial-data output. dout changes state on the falling edge of sclk . dout is high impedance when oe is high. 10 10 sclk serial-clock input. sclk drives the conversion process and clocks data out. acquisition ends on the 3rd falling edge after the cs falling edge. the lsb is clocked out on the sclk 15th falling edge and the device enters autoshutdown mode (see figures 8 , 9, and 10). ep exposed pad. not internally connected. connect the exposed pad to gnd or leave floating. pin description dout v dd ref 12-bit sar adc cs sclk oe gnd output shift register control logic and timing *indicates the max1396 ain+ (ain1)* ain- (ain2)* input mux and t/h uni/bip (ch1/ch2)* max1393 max1396 figure 3. simplified functional diagram
and the difference between the sampled positive and negative input voltages is converted. the time required for the t/h to acquire an input signal is determined by how quickly its input capacitance is charged. the required acquisition time lengthens as the input signal? source impedance increases. the acquisition time, t acq , is the minimum time needed for the signal to be acquired. it is calculated by the following equation: t acq 9 x (r source + r in ) x c in + t pu where: r source is the source impedance of the input signal. r in = 500 ? , which is the equivalent differential analog input resistance. c in = 16pf, which is the equivalent differential analog input capacitance. t pu = 400ns. note: t acq is never less than 600ns and any source impedance below 400 ? does not significantly affect the adc? ac performance. analog input bandwidth the adc? input-tracking circuitry has a 4mhz full- power bandwidth, making it possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest. analog input range and protection the max1393/max1396 produce a digital output that corresponds to the analog input voltage as long as the analog inputs are within their specified range. when operating the max1393 in unipolar mode (uni/ bip = 1), the specified differential analog input range is from 0 to v ref . when operating in bipolar mode (uni/ bip = 0), the differential analog input range is from -v ref /2 to +v ref /2 with a common-mode range of 0 to v dd . the max1396 has an input range from 0 to v ref . internal protection diodes confine the analog input volt- age within the region of the analog power input rails (v dd , gnd) and allow the analog input voltage to swing from gnd - 0.3v to v dd + 0.3v without damage. input voltages beyond gnd - 0.3v and v dd + 0.3v forward bias the internal protection diodes. in this situation, limit the forward diode current to less than 50ma to avoid damage to the max1393/max1396. output data format figures 8, 9, and 10 illustrate the conversion timing for the max1393/max1396. sixteen sclk cycles are required to read the conversion result and data on dout transitions on the falling edge of sclk. the con- version result contains 4 zeros, followed by 12 data bits with the data in msb-first format. for the max1393, data is straight binary for unipolar mode and two? comple- ment for bipolar mode. for the max1396, data is always straight binary. transfer function figure 5 shows the unipolar transfer function for the max1393/max1396. figure 6 shows the bipolar trans- fer function for the max1393. code transitions occur halfway between successive-integer lsb values. max1393/max1396 _______________________________________________________________________________________ 9 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs + - hold track cin+ ref gnd dac cin- rin+ rin- v dd /2 r source comparator hold hold ain2 a in 1 (ain+)* gnd (ain-)* analog signal source max1393 max1396 *indicates the max1393 figure 4. equivalent input circuit
max1393/max1396 applications information starting a conversion a falling edge on cs initiates the power-up sequence and begins acquiring the analog input as long as oe is also asserted low. on the 3rd sclk falling edge, the analog input is held for conversion. the most significant bit (msb) decision is made and clocked onto dout on the 4th sclk falling edge. valid dout data is available to be clocked into the master (microcontroller (?)) on the following sclk rising edge. the rest of the bits are decided and clocked out to dout on each successive sclk falling edge. see figures 8 and 9 for conversion timing diagrams. once a conversion has been initiated, cs can go high at any time. further falling edges of cs do not reinitiate an acquisition cycle until the current conversion completes. once a conversion completes, the first falling edge of cs begins another acquisition/conversion cycle. selecting unipolar or bipolar mode (max1393 only) drive uni/ bip high to select unipolar mode or pull uni/ bip low to select bipolar mode. uni/ bip can be connected to v dd for logic high, to gnd for logic low, or actively driven. uni/ bip needs to be stable for t ubs prior to the first rising edge of sclk after the cs falling edge (see figure 1) for a valid conversion result when being actively driven. selecting analog input ain1 or ain2 (max1396 only) pull ch1 /ch2 low to select ain1 or drive ch1 /ch2 high to select ain2 for conversion. ch1 /ch2 can be connected to v dd for logic high, to gnd for logic low, or actively driven. ch1 /ch2 needs to be stable for t chs prior to the first rising edge of sclk after the cs falling edge (see figure 1) for a valid conversion result when being actively driven. 10 ______________________________________________________________________________________ 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs zs = 0 fs = v ref 1 lsb = v ref 4096 fs fff ffe ffc ffb 000 001 003 004 output code (hex) input voltage (lsb) ffd 0 1234 fs - 1.5 lsb full-scale transition 002 figure 5. unipolar transfer function zs = 0 +fs = v ref 2 -fs = -v ref 2 1 lsb = v ref 4096 -fs +fs 7ff 7fe 001 000 800 801 ffe output code (hex) input voltage (lsb) fff 0 +fs - 1.5 lsb -fs + 0.5 lsb full-scale transition figure 6. bipolar transfer function
autoshutdown mode the adc automatically powers down on the sclk falling edge that clocks out the lsb. this is the falling edge after the 15th sclk. dout goes low when the lsb has been clocked into the master (?) on the 16th rising sclk edge. alternatively, drive oe high to force the max1393/ max1396 into power-down. whenever oe goes high, the adc powers down and disables dout regardless of cs , sclk, or the state of the adc. dout enters a high-impedance state after t dod . external reference the max1393/max1396 use an external reference between 0.6v and (v dd + 50mv). bypass ref with a 0.1? capacitor to gnd for best performance (see the typical operating circuit ). serial interface the max1393/max1396 serial interface is fully compati- ble with spi, qspi, and microwire (see figure 7). if a serial interface is available, set the ?? serial interface in master mode so the ? generates the serial clock. choose a clock frequency between 100khz and 5mhz. cs and oe can be connected together and driven simultaneously. oe can also be connected to gnd if the dout bus is not shared and driven independently. spi and microwire when using spi or microwire, make the ? the bus master and set cpol = 0 and cpha = 0 or cpol = 1 and cpha = 1. (these are the bits in the spi or microwire control register.) two consecutive 1-byte reads are required to get the entire 12-bit result from the adc. dout transitions on sclk? falling edge and is clocked into the ? on the sclk? rising edge. see figure 7 for connections and figures 8 and 9 for timing diagrams. the conversion result contains 4 zeros, fol- lowed by the 12 data bits with the data in msb-first for- mat. when using cpol = 0 and cpha = 0 or cpol = 1 and cpha = 1, the msb of the data is clocked into the ? on the sclk? fifth rising edge. to be compatible with spi and microwire, connect cs and oe togeth- er and drive simultaneously. qspi unlike spi, which requires two 1-byte reads to acquire the 12 bits of data from the adc, qspi allows the mini- mum number of clock cycles necessary to clock in the data. however, the max1393/max1396 require 16 clock cycles from the ? to clock out the 12 bits of data. see figure 7 for connections and figures 8 and 9 for timing diagrams. the conversion result contains 4 zeros, followed by the 12 data bits with the data in msb-first format. when using cpol = 0 and cpha = 0 or cpol = 1 and cpha = 1, the msb of the data is clocked into the ? on the sclk? fifth rising edge. to be compatible with qspi, connect cs and oe together and drive simultaneously. dsp interface figure 10 shows the timing for dsp operation. figure 11 shows the connections between the max1393/ max1396 and several common dsps. max1393/max1396 ______________________________________________________________________________________ 11 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs max1393 max1396 oe a) spi i/o sck cs dout miso i/o uni/bip (ch1/ch2)* sclk max1393 max1396 oe cs sck cs dout miso i/o uni/bip (ch1/ch2)* sclk max1393 max1396 oe i/o sk cs dout si i/o uni/bip (ch1/ch2)* sclk b) qspi c) microwire *indicates the max1396 figure 7. common serial-interface connections to the max1393/max1396
max1393/max1396 12 ______________________________________________________________________________________ 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs adc s tate bipolar (ain1) * uni (ain2) * 1234567891011 12 13 14 15 16 1 sclk high-z high-z dout d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 power- down power- down sampling instant uni/bip (ch1/ch2)* cs = oe power-up and acquire (t acq ) hold and convert (t conv ) *indicates the max1396 figure 8. serial-interface timing for spi/qspi (cpol = cpha = 1) and microwire (g6 = 0, g5 = 1) adc s tate bipolar (ain1)* uni (ain2)* 1234567891011 12 13 14 15 16 1 sclk high-z high-z dout d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 power- down power- down sampling instant uni/bip ( ch1 /ch2)* cs = oe power-up and acquire (t acq ) hold and convert (t conv ) *indicates the max1396 figure 9. serial-interface timing for spi/qspi (cpol = cpha = 0) and microwire (g6 = 0, g5 = 0)
as shown in figure 11, drive the max1393/max1396 chip-select input ( cs ) with the dsp? frame-sync signal. oe may be connected to gnd or driven independently. for continuous conversion operation, keep oe low and make the cs falling edge coincident with the 16th falling edge of the sclk. unregulated two-cell or single lithium limno 2 cell operation low operating voltage (1.5v to 3.6v) and ultra-low-power consumption make the max1393/max1396 ideal for low cost, unregulated, battery-powered applications without the need for a dc-dc converter. power the max1393/ max1396 directly from two alkaline/nimh/nicd cells in series or a single lithium coin cell as shown in the typical operating circuit . fresh alkaline cells have a voltage of approximately 1.5v per cell (3v with 2 cells in series) and approach end of life at 0.8v (1.6v with 2 cells in series). a typical 2xaa alkaline discharge curve is shown in figure 12a. a typical cr2032 lithium (limno 2 ) coin cell discharge curve is shown in figure 12b. layout, grounding, and bypassing for best performance, use pc boards. board layout must ensure that digital and analog signal lines are separated from each other. do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 13 shows the recommended system ground connections. establish a single-point analog ground (star ground point) at the max1393/max1396s?gnd pin or use the ground plane. high-frequency noise in the power supply (v dd ) degrades the adc? performance. bypass v dd to gnd with a 0.1? capacitor as close to the device as possi- ble. minimize capacitor lead lengths for best supply noise rejection. to reduce the effects of supply noise, a 10 ? resistor can be connected as a lowpass filter to attenuate supply noise. exposed pad the max1393/max1396 tdfn package has an exposed pad on the bottom of the package. this pad is not internally connected. connect the exposed pad to the gnd pin on the max1393/max1396 or leave float- ing for proper electrical performance. definitions integral nonlinearity (inl) inl is the deviation of the values on an actual transfer function from a straight line. for the max1393/ max1396, this straight line is between the end points of the transfer function once offset and gain errors have been nullified. inl deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics section. max1393/max1396 ______________________________________________________________________________________ 13 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs adc s tate bipolar (ain1)* uni (ain2)* 1 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 fs 2 1 sclk dout d11 d0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 power- down power- down sampling instant cs oe power-up and acquire (t acq ) hold and convert (t conv ) uni/bip ( ch1 /ch2)* *indicates the max1396 figure 10. dsp serial-timing diagram
max1393/max1396 differential nonlinearity (dnl) dnl is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than ? lsb guarantees no missing codes and a monotonic transfer function. for the max1393/ max1396, dnl deviations are measured at every step and the worst-case deviation is reported in the electrical characteristics section. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise plus the rms distortion. rms noise includes all spectral components to the nyquist frequency excluding the fundamental, the first five har- monics (hd2?d5), and the dc offset. rms distortion includes the first five harmonics (hd2?d5): sinad signal noise distortion rms rms rms log = + ? ? ? ? ? ? ? ? ? ? ? ? 20 22 14 ______________________________________________________________________________________ 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs max1393 max1396 oe a) tms320c541 connection diagram i/o fsx fsr cs dout dr i/o uni/bip (ch1/ch2)* clkx clkr sclk max1393 max1396 oe b) adsp218x connection diagram i/o tfs rfs cs dout dr i/o uni/bip (ch1/ch2)* sclk sclk max1393 max1396 oe c) dsp563xx connection diagram *indicates the max1396 i/o sc2 cs dout i/o uni/bip (ch1/ch2)* slk sdr sclk figure 11. common dsp connections to the max1393/max1396 days voltage (v) 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1.6 0 700 600 500 400 300 200 100 t a = +25 c figure 12a. typical 2xaa discharge curve at 100ksps days voltage (v) 40 30 20 10 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1.6 050 t a = +25 c figure 12b. typical cr2032 discharge curve at 100ksps
signal-to-noise ratio (snr) snr is a dynamic figure of merit that indicates the con- verter? noise performance. for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr db[max] = 6.02 db x n + 1.76 db in reality, there are other noise sources such as thermal noise, reference noise, and clock jitter that also degrade snr. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the fundamental, the first five harmonics, and the dc offset. total harmonic distortion (thd) thd is a dynamic figure of merit that indicates how much harmonic distortion the converter adds to the signal. thd is the ratio of the rms sum of the first five harmon- ics of the fundamental signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 6 are the amplitudes of the 2nd- through 6th-order harmonics. spurious-free dynamic range (sfdr) sfdr is a dynamic figure of merit that indicates the lowest usable input signal amplitude. sfdr is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest spurious component, excluding dc offset. sfdr is specified in decibels relative to the carrier (dbc). intermodulation distortion (imd) imd is the ratio of the rms sum of the intermodulation products to the rms sum of the two fundamental input tones. this is expressed as: the fundamental input tone amplitudes (v 1 and v 2 ) are at -6.5dbfs. fourteen intermodulation products (v im _) are used in the max1393/max1396 imd calculation. the intermodulation products are the amplitudes of the output spectrum at the following frequencies, where f in1 and f in2 are the fundamental input tone frequencies: 2nd-order intermodulation products: f in1 + f in2 , f in2 - f in1 3rd-order intermodulation products: 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 4th-order intermodulation products: 3 x f in1 - f in2 , 3 x f in2 - f in1 , 3 x f in1 + f in2 , 3 x f in2 + f in1 5th-order intermodulation products: 3 x f in1 - 2 x f in2 , 3 x f in2 - 2 x f in1 , 3 x f in1 + 2 x f in2 , 3 x f in2 + 2 x f in1 channel-to-channel crosstalk channel-to-channel crosstalk indicates how well each analog input is isolated from the others. the channel-to- channel crosstalk for the max1396 is measured by applying dc to channel 2 while an ac sine wave is applied to channel 1. an fft is taken for channel 1 and channel 2 and the difference (in db) is reported as the channel-to-channel crosstalk. aperture delay the max1393/max1396 sample data on the falling edge of its third sclk cycle (figure 14). in actuality, there is a small delay between the falling edge of the sampling clock and the actual sampling instant. aperture delay (t ad ) is the time defined between the imd vv v v vv im im im imn log ..... = ++++ + ? ? ? ? ? ? ? ? 20 1 2 2 2 3 22 1 2 2 2 thd vvvvv v log = ++++ ? ? ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 1 max1393/max1396 ______________________________________________________________________________________ 15 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs 10 ? (optional) v dd v dd power supply gnd digital circuitry gnd dgnd d ata star ground point dv dd v dd max1393/max1396 figure 13. power-supply grounding connections
max1393/max1396 falling edge of the sampling clock and the instant when an actual sample is taken. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the aperture delay (figure 14). dc power-supply rejection ratio (psrr) dc psrr is defined as the change in the positive full- scale transfer function point caused by a full range vari- ation in the analog power-supply voltage (v dd ). chip information transistor count: 9106 process: bicmos 16 ______________________________________________________________________________________ 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs t ad t/h (internal signal) sclk t aj track hold analog input sampled d ata third falling edge figure 14. t/h aperture timing ain+ (ain1)* dout sclk ain- (ain2)* ref differential input voltage 2 x aa cells cpu + - v dd gnd ref input voltage 0.1 f 0.1 f cs oe uni/ bip ( ch1 /ch2)* miso scl ss max1393 max1396 *indicates the max1396 only. t ypical operating circuit
max1393/max1396 ______________________________________________________________________________________ 17 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs 1 2 3 4 5 max 10 9 8 7 6 sclk dout cs oe gnd ain+ ain- v dd max1393 top view ref uni/bip cs oe uni/bip gnd ref 1 2 3 4 5 10 98 7 6 sclk dout ain- ain+ v dd 3mm x 3mm tdfn top view max1393 1 2 3 4 5 max 10 9 8 7 6 sclk dout cs oe gnd ain1 ain2 v dd max1396 top view ref ch1/ch2 top view cs oe ch1/ch2 gnd ref 1 2 3 4 5 10 98 7 6 sclk dout ain2 ain1 v dd 3mm x 3mm tdfn max1396 pin configurations
package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) max1393/max1396 18 ______________________________________________________________________________________ 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs 6, 8, &10l, dfn thin.eps l c l c pin 1 index area d e l e l a e e2 n g 1 2 21-0137 package outline, 6,8,10 & 14l, tdfn, exposed pad, 3x3x0.80 mm -drawing not to scale- k e [(n/2)-1] x e ref. pin 1 id 0.35x0.35 detail a b d2 a2 a1 common dimensions symbol min. max. a 0.70 0.80 d 2.90 3.10 e 2.90 3.10 a1 0.00 0.05 l 0.20 0.40 pkg. code n d2 e2 e jedec spec b [(n/2)-1] x e package variations 0.25 min. k a2 0.20 ref. 2.300.10 1.500.10 6 t633-1 0.95 bsc mo229 / weea 1.90 ref 0.400.05 1.95 ref 0.300.05 0.65 bsc 2.300.10 8 t833-1 2.00 ref 0.250.05 0.50 bsc 2.300.10 10 t1033-1 2.40 ref 0.200.05 - - - - 0.40 bsc 1.700.10 2.300.10 14 t1433-1 1.500.10 1.500.10 mo229 / weec mo229 / weed-3 0.40 bsc - - - - 0.200.05 2.40 ref t1433-2 14 2.300.10 1.700.10 t633-2 6 1.500.10 2.300.10 0.95 bsc mo229 / weea 0.400.05 1.90 ref t833-2 8 1.500.10 2.300.10 0.65 bsc mo229 / weec 0.300.05 1.95 ref t833-3 8 1.500.10 2.300.10 0.65 bsc mo229 / weec 0.300.05 1.95 ref -drawing not to scale- g 2 2 21-0137 package outline, 6,8,10 & 14l, tdfn, exposed pad, 3x3x0.80 mm downbonds allowed no no no no yes no yes no
max1393/max1396 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 1.5v to 3.6v, 312.5ksps, 1-channel true-differential/ 2-channel single-ended, 12-bit, sar adcs 10lumax.eps package outline, 10l umax/usop 1 1 21-0061 i rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min - a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 ? 0.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1

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